Field programmable gate array and communication method
US11586572B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2016 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jan 5, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17792
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The application provides a field programmable gate array (FPGA) and a communication method. At least one application specific integrated circuit based (ASIC-based) hard core is embedded in the FPGA. The ASIC-based hard core includes a high-speed exchange and interconnection unit and at least one station. Each station is connected to the high-speed exchange and interconnection unit. The station is configured to transmit data between each functional module in the FPGA and the ASIC-based hard core. The high-speed exchange and interconnection unit is configured to transmit data between the stations. In the FPGA provided by the application, an ASIC-based hard core is embedded, which can facilitate data exchange between each functional module and the ASIC-based hard core in proximity and reduce a time delay.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.