Avoiding electrostatic discharge events from cross-hierarchy tie nets
US11586798B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 13, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Aug 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system is configured to avoid establishing an electrostatic discharge (ESD) region in an integrated circuit (IC). The system includes a processor and memory storing an IC simulator. The IC simulator establishes an IC chip that is sub-divided into a plurality of hierarchical levels. The IC simulator further analyzes a first hierarchical level to determine first connectivity information indicating connectivity between the first hierarchical level and one or both of lower-level pins and lower-level nets of a targeted hierarchical level having a lower-level of hierarchy with respect to the first hierarchical level and analyzes the targeted hierarchical level to determine second connectivity information indicating diode connectivity to one or both high-level pins and higher-level nets included in the first hierarchical level. The IC simulator determines an ESD fail region mitigation operation configured to avoid establishing the ESD region based on the first connectivity information and the second connectivity information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.