Arithmetic unit for deep learning acceleration
US11586907B2 · kind B2 · utility
5Cited by
10References
22Claims
0Family size
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Key dates
| Filing date | Feb 20, 2019 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Dec 24, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N20/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a device include an integrated circuit, a reconfigurable stream switch formed in the integrated circuit, and an arithmetic unit coupled to the reconfigurable stream switch. The arithmetic unit has a plurality of inputs and at least one output, and the arithmetic unit is solely dedicated to performance of a plurality of parallel operations. Each one of the plurality of parallel operations carries out a portion of the formula: output=AX+BY+C.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.