Memory having flying bitlines for improved burst mode read operations
US11587610B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | May 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4097
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory systems having flying bitlines for improved burst mode read operations and related methods are provided. A memory system comprises a memory array including a first set of memory cells coupled to a first inner wordline and a second set of memory cells coupled to a first outer wordline. The memory system includes a control unit configured to generate control signals for simultaneously: asserting a first wordline signal on the first inner wordline coupled to each of a plurality of inner bitlines, and asserting a second wordline signal on the first outer wordline coupled to each of a plurality of outer bitlines, where each of the plurality of outer bitlines includes a first portion configured to fly over or fly under a corresponding inner bitline, and outputting data from each of the first set of memory cells and the second set of memory cells as part of a burst.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.