Semiconductor fabrication tool having gas manifold assembled by jig
US11587802B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | May 8, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67126
- WIPO fieldSurface technology, coating
- WIPO sectorChemistry
Abstract
A method of processing a semiconductor wafer is provided. The method includes installing upper lid. The installation of the upper lid includes placing an inlet manifold on a water box; inserting a jig into a lower gas channel in the water box and inserting into an upper gas channel in the inlet manifold; fastening the water box to the inlet manifold; and removing the jig after the water box engaging with the inlet manifold. The method also includes connecting a shower head on a lower side of the water box; and connecting the upper lid to a housing. The method further includes placing a semiconductor wafer into the housing. In addition, the method includes supplying a process gas over the semiconductor wafer through the upper gas channel, the lower gas channel and the shower head.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.