Forming metal plug through a hole in a device including a resistance layer and contacting embedded conductive structures
US11587848B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Apr 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5228
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.