Semiconductor memory device
US11587868B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Sep 2, 2021 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Sep 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a substrate; a plurality of first conductive layers arranged in a first direction; a first semiconductor column; a first bit line being disposed at a position overlapping the first semiconductor column viewed in the first direction; a first wiring including a part overlapping the first bit line viewed in the first direction; and a second wiring including a part overlapping the first bit line viewed in the first direction. When a period in which a voltage of the first wiring transitions from a high to a low voltage state is assumed to be a first period, and when a period in which a voltage of the second wiring transitions from a low to a high voltage state is assumed to be a second period, at least a part of the second period overlaps at least a part of the first period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.