Multi-layer semiconductor package with stacked passive components
US11587899B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Jul 29, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first layer including a semiconductor die embedded within a dielectric substrate, and a first set of metal pillars extending through the dielectric substrate, a second layer stacked on the first layer, the second layer including a metal trace patterned on the dielectric substrate of the first layer, a passive component including at least one capacitor or resistor electrically coupled to the metal trace, and a second set of metal pillars extending from the metal trace to an opposing side of the second layer, and a third layer stacked on the second layer, the third layer including at least one inductor electrically coupled to metal pillars of the second set of metal pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.