Semiconductor devices
US11588035B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 20, 2020 |
| Grant date | Feb 21, 2023 |
| Priority date | — |
| Expiry date | Nov 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
Abstract
A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked in the first region and forming a pad region having a stepped shape extending by different lengths in the second region, interlayer insulating layers alternately stacked with the gate electrodes, channel structures passing through the gate electrodes in the first region and including a channel layer, separation regions passing through the gate electrodes in the first and second regions, an etch-stop layer disposed on uppermost gate electrodes, among the gate electrodes forming the pad region in the second region, not to overlap the first region and the separation regions, a cell region insulating layer covering the gate electrodes and the etch-stop layer, and contact plugs passing through the cell region insulating layer and the etch-stop layer in the second region and connected to the gate electrodes in the pad region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.