Wafer level ultrasonic chip module and manufacturing method thereof
US11590536B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Feb 13, 2019 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Sep 24, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N30/501
- WIPO fieldChemical engineering
- WIPO sectorChemistry
Abstract
A wafer level ultrasonic chip module includes a substrate, a composite layer, a conducting material, and a base material. The substrate has a through slot that passes through an upper surface of the substrate and a lower surface of the substrate. The composite layer includes an ultrasonic body and a protective layer. A lower surface of the ultrasonic body is exposed from the through slot. The protective layer covers the ultrasonic body and a partial upper surface of the substrate. The protective layer has an opening, from which a partial upper surface of the ultrasonic body is exposed. The conducting material is in contact with the upper surface of the ultrasonic body. The base material covers the through slot, such that a space is formed among the through slot, the lower surface of the ultrasonic body and an upper surface of the base material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.