Readout circuit layout structure and method of reading data
US11594264B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 21, 2022 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jul 21, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/005
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to the field of semiconductor circuit design, and in particular to a readout circuit layout structure and a method of reading data. The readout circuit layout structure includes: a first readout circuit structure and a second readout circuit structure having identical structures, wherein the first readout circuit structure and the second readout circuit structure each include: a first isolation module, configured to be turned on according to a first isolation signal, electrically connect a bit line and a first readout bit line, and electrically connect a complementary bit line and a first complementary readout bit line; a second isolation module, configured to be turned on according to a second isolation signal, electrically connect the first readout bit line and a second readout bit line, and electrically connect the first complementary readout bit line and a second complementary readout bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.