Memory controller physical interface with differential loopback testing
US11594296B2 · kind B2 · utility
1Cited by
2References
19Claims
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Key dates
| Filing date | Mar 18, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Apr 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Systems, apparatus and methods are provided for loopback testing techniques for memory controllers. A memory controller that may comprise loopback testing circuitry that may comprise a first multiplexer having a first input coupled to an output of an input buffer and a second input coupled to a first data output from the memory controller, an inverter coupled to the output of the input buffer, and a second multiplexer having a first input coupled to an output of the inverter and a second input coupled to a second data output from the memory controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.