Chip package and electronic device
US11594465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 24, 2021 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jul 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/1623
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The disclosure provides a chip package and an electronic device. The chip package includes: a package substrate, a semiconductor substrate provided on the package substrate and a first chip and a second chip provided on the semiconductor substrate. The semiconductor substrate includes a first group of pins and a second group of pins arranged on the semiconductor substrate and a connecting layer located between the first group of pins and the second group of pins. The connecting layer has a plurality of connecting channels, and the first group of pins and the second group of pins are connected through the plurality of connecting channels. The first chip has a third group of pins, the second chip has a fourth group of pins, and the third group of pins are connected to the first group of pins, and the fourth group of pins are connected to the second group of pins.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.