VCSEL array layout
US11594860B2 · kind B2 · utility
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11References
6Claims
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Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jul 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01S5/0042
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An array layout of VCSELs is intentionally mis-aligned with respect to the xy-plane of the device structure as defined by the crystallographic axes of the semiconductor material. The mis-alignment may take the form of skewing the emitter array with respect to the xy-plane, or rotating the emitter array. In either case, the layout pattern retains the desired, row/column structure (necessary for dicing the structure into one-dimensional arrays) while reducing the probability that an extended defect along a crystallographic plane will impact a large number of individual emitters.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.