Ramp generator providing high resolution fine gain including fractional divider with delta-sigma modulator
US11595030B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 5, 2020 |
| Grant date | Feb 28, 2023 |
| Priority date | — |
| Expiry date | Jan 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A ramp generator providing ramp signal with high resolution fine gain includes a current mirror having a first and second paths to conduct a capacitor current and an integrator current responsive to the capacitor current. First and second switched capacitor circuits are coupled to the first path. A fractional divider circuit is coupled to receive a clock signal to generate in response to an adjustable fractional divider ratio K a switched capacitor control signal that oscillates between first and second states to control the first and second switched capacitor circuits. The first and second switched capacitor circuits are coupled to be alternatingly charged by the capacitor current and discharged in response to each the switched capacitor control signal. An integrator coupled is to the second path to generate the ramp signal in response to the integrator current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.