Flushing a fetch queue using predecode circuitry and prediction information
US11599361B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2021 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | May 10, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing apparatus is provided. It includes control flow detection prediction circuitry that performs a presence prediction of whether a block of instructions contains a control flow instruction. A fetch queue stores, in association with prediction information, a queue of indications of the instructions and the prediction information comprises the presence prediction. An instruction cache stores fetched instructions that have been fetched according to the fetch queue. Post-fetch correction circuitry receives the fetched instructions prior to the fetched instructions being received by decode circuitry, the post-fetch correction circuitry includes analysis circuitry that causes the fetch queue to be at least partly flushed in dependence on a type of a given fetched instruction and the prediction information associated with the given fetched instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.