Patent · US Active

Memory system capable of performing a bit partitioning process and an internal computation process

US11600319B2 · kind B2 · utility

2Cited by

1References

10Claims

0Family size

Assignee

NATIONAL CHENG KUNG UNIVERSITY · TW

Inventors

Lih-Yih Chiou · Tainan, TW
Yu-Wei Lin · Kaohsiung, TW
Wei Ling · Beijing, CN

Key dates

Filing date	Jun 18, 2021
Grant date	Mar 7, 2023
Priority date	—
Expiry date	Jun 23, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/419
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory system includes a plurality of first memory units, a plurality of read word lines, and a plurality of read bit lines. Each first memory unit of the plurality of first memory units includes a second memory unit, a first transistor coupled to the second memory unit, and a second transistor coupled to the second memory unit and the first transistor. Each read word line of the plurality of read word lines is coupled to a plurality of first transistors disposed along a corresponding row. Each read bit line of the plurality of read bit lines is coupled to a plurality of second transistors disposed along a corresponding column.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.