Methods of testing nonvolatile memory devices
US11600350B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a method of testing a nonvolatile memory device including a first semiconductor layer in which and a second semiconductor layer is formed prior to the first semiconductor layer, circuit elements including a page buffer circuit are provided in the second semiconductor layer, an on state of nonvolatile memory cells which are not connected to the page buffer circuit is mimicked by providing a conducting path between an internal node of a bit-line connection circuit connected between a sensing node and a bit-line node of the page buffer circuit and a voltage terminal to receive a first voltage, a sensing and latching operation with the on state being mimicked is performed in the page buffer circuit and a determination is made as to whether the page buffer circuit operates normally is made based on a result of the sensing and latching operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.