Storage device
US11600352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 2021 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Aug 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage device includes a memory, a write circuit, a read circuit, and a debug information register. The memory includes a data area and a redundant area that corresponds to the data area. The write circuit writes first data specified in a write command to the data area, and first information about a transmission source which has transmitted the write command, to the redundant area. The read circuit reads the first data as second data from the data area, and reads the first information as second information from the redundant area, in response to a read command. The debug information register stores the second information read by the read circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.