Semiconductor structure and method for forming the same
US11600528B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2020 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Dec 2, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0128
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A method for forming a semiconductor structure is provided. The method includes forming a stack over a substrate. The stack includes alternating first semiconductor layers and second semiconductor layers. The method also includes forming a polishing stop layer over the stack and a dummy layer over the polishing stop layer, recessing the dummy layer, the polishing stop layer and the stack to form a recess, forming a third semiconductor layer to fill the recess, and planarizing the dummy layer and the third semiconductor layer until the polishing stop layer is exposed. The method also includes patterning the polishing stop layer and the stack into a first fin structure and the third semiconductor layer into a second fin structure, removing the second semiconductor layers of the first fin structure to form nanostructures, and forming a gate stack across the first fin structure and the second fin structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.