Semiconductor memory device and method of fabricating the same
US11600570B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 2020 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Feb 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.