Three-dimensional semiconductor memory devices and methods of fabricating the same
US11600638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2020 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Jan 29, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are three-dimensional semiconductor memory devices and methods of fabricating the same. The method comprises sequentially forming a sacrificial pattern and a source conductive layer on a substrate, forming a mold structure including a plurality of insulating layers and a plurality of sacrificial layers on the source conductive layer; forming a plurality of vertical structures penetrating the mold structure, forming a trench penetrating the mold structure, forming a sacrificial spacer on a sidewall of the trench, removing the sacrificial pattern to form a horizontal recess region; removing the sacrificial spacer, and forming a source conductive pattern filling the horizontal recess region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.