High efficient microdevices
US11600743B2 · kind B2 · utility
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15References
16Claims
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Assignee
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Key dates
| Filing date | May 31, 2019 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | May 31, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10H29/142
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A microdevice structure comprising at least part of an edge of a microdevice is covered with a metal-insulator-semiconductor (MIS) structure, wherein the MIS structure comprises a MIS dielectric layer and a MIS gate conductive layer, at least one gate pad provided to the MIS gate conductive layer, and at least one micro device contact extended upwardly on a top surface of the micro device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.