Connection terminal pattern and layout for three-level buck regulator
US11601051B2 · kind B2 · utility
1Cited by
3References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Mar 7, 2023 |
| Priority date | — |
| Expiry date | Nov 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/1586
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure generally relate to a connection terminal pattern and layout for a three-level buck regulator. One example electronic module generally includes a substrate, an integrated circuit (IC) package disposed on the substrate and comprising transistors of a three-level buck regulator, a capacitive element of the three-level buck regulator disposed on the substrate, and an inductive element of the three-level buck regulator disposed on the substrate. In certain aspects, the capacitive element and the inductive element may be disposed adjacent to different sides of the IC package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.