Multiple power management integrated circuits and apparatus having dual pin interface
US11604485B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 7, 2022 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Feb 7, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02M3/157
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.