Compute system with controller area network error protection mechanism and method of operation thereof
US11605251B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Apr 15, 2020 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | May 8, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/40273
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method of operation of a compute system comprising: operating a controller area network with a first node including a first error counter and a second node including a second error counter; transmitting a message from the first node to the second node over the controller area network; detecting an error by the first node or the second node; incrementing the first error counter or the second error counter based on whichever the first node or the second node that detected the error; and shutting off an on-board diagnostic port when the first error counter or the second error counter reaches a shut-off threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.