Host processor, display system including the host processor, and method of operating the display system
US11605334B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jan 19, 2022 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Jan 19, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2370/20
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A host processor includes a high-speed driver which generates first high-speed data, a coupling circuit which receives the first high-speed data from the high-speed driver, and removes a direct-current (“DC”) component of the first high-speed data to generate second high-speed data, a low-power driver which generates low-power data, and a passive switch which receives the second high-speed data from the coupling circuit, receives the low-power data from the low-power driver, and selectively outputs the second high-speed data or the low-power data to a display apparatus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.