Display panel and pixel circuit
US11605352B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 8, 2022 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Jul 8, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2320/045
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided is a display panel including n pixel sets. Each pixel set includes 2m pixel rows arranged along a first direction. n and m are positive integers. Each pixel row includes pixel circuits arranged along a second direction intersecting with the first direction. Each pixel circuit includes a driving transistor, a first reset module configured to transmit, in response to a first scan signal provided by a first scan signal line, a first reset signal provided by a first reset signal line to a gate electrode of the driving transistor, and a second reset module configured to transmit, in response to a second scan signal provided by a second scan signal line, a second reset signal provided by a second reset signal line to an anode of an organic light-emitting element. The gate electrode receives high and low levels that are configured to reset the gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.