Memory systems having memory devices therein with enhanced error correction capability and methods of operating same
US11605441B1 · kind B1 · utility
1Cited by
10References
23Claims
0Family size
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Key dates
| Filing date | Aug 30, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Aug 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/1204
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory module having a plurality of memory devices therein. A memory controller is configured to transmit commands and addresses to the memory module in synchronization with a clock, input/output data to and from the memory module in synchronization with a data transfer clock, and perform system error correction operations on data read from the memory module. The plurality of memory devices perform on-die error correction operations, which are different from each other according to a physical location of the stored read data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.