Transistors with multiple threshold voltages
US11605638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Jun 11, 2041 |
Classification
- Technology area (CPC B)Performing Operations; Transporting
- CPC primaryB82Y10/00
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
Semiconductor structures and methods are provided. A method according to the present disclosure includes forming a first channel member, a second channel member directly over the first channel member, and a third channel member directly over the second channel member, depositing a first metal layer around each of the first channel member, the second channel member, and the third channel member, removing the first metal layer from around the second channel member and the third channel member while the first channel member remains wrapped around by the first metal layer, after the removing of the first metal layer, depositing a second metal layer around the second channel member and the third channel member, removing the second metal layer from around the third channel member, and after the removing of the second metal layer, depositing a third metal layer around the third channel member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.