Fault detection within an analog-to-digital converter
US11606099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 23, 2021 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Sep 23, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/122
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes an analog-to-digital converter (ADC) having selectable first and second analog channel inputs and a digital output. A window comparator coupled to the digital output. The window comparator configured to compare a digital value on the digital output to first and second threshold values. A programmable clock circuit configured to provide a clock signal to the ADC. A controller that, response to assertion of the trigger signal, is configured to generate a sample rate control signal to the clock circuit to cause the clock circuit to increase the frequency of the clock signal and toggle selection between the first and second analog channel inputs. A result comparison circuit having a comparison input coupled to the digital output. The result comparison circuit is configured to compare a first digital conversion output from the ADC to a second digital conversion output from the ADC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.