Clock synchronization
US11606156B1 · kind B1 · utility
3Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Mar 14, 2023 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A method, system, and apparatus for determining delay between clocks, in response to a trigger event, buffering DSP symbol information in a symbol capture buffer; wherein the amount of DSP symbol information buffered corresponds to the amount of symbols captured during a buffer storage interval; and extracting a synchronization packet from the symbol capture buffer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.