Wireline transceiver with internal and external clock generation
US11609597B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Dec 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L1/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit device, having functional circuitry driven by a clock signal, includes a first clock path for accepting an external clock signal where the first clock path includes first biasing circuitry configured to controllably pass the external clock signal, a second clock path for accepting an external frequency reference signal where the second clock path includes internal clock generation circuitry configured to generate an internal clock signal from the external frequency reference signal and second biasing circuitry configured to controllably pass the external frequency reference signal to the internal clock generation circuitry, and selector circuitry configured to select, based on user input, a clock output to drive the functional circuitry of the integrated circuit device. The clock output is selected from between (i) an output of the first clock path, and (ii) an output of the second clock path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.