Electronic device with multiple processors and synchronization method thereof
US11609599B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 25, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Oct 25, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device comprises a first processor, a second processor and a communication interface. The first processor operates according to a first clock, and comprises a first time-stamp counter to count the first clock to obtain a first count value. The second processor operates according to a second clock, and comprises a second time-stamp counter to count the second clock to obtain a second count value. The communication interface is coupled between the first processor and the second processor. The first processor periodically sends the first count value to the second processor through the communication interface. When the second processor receives the first count value, the second processor adds a preset deviation value to the first count value to obtain a synchronization value, resets the second count value, and the sum of the synchronization value and the second count value is read by the second processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.