Patent · US Active

Memory controller system and a method for memory scheduling of a storage device

US11609709B2 · kind B2 · utility

1Cited by

0References

15Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Chee Hak Teh · Kampung Bukit Kechil, MY
Yu Ying Ong · Ampang Jaya, MY

Key dates

Filing date	Jan 5, 2021
Grant date	Mar 21, 2023
Priority date	—
Expiry date	Jul 2, 2041

Classification

Technology area (CPC Y)Emerging Cross-Sectional Technologies
CPC primaryY02D10/00
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory controller system comprising a scheduling module, a data buffer module, a global order buffer module and a linked-list controlling module. The linked-list controlling module is configured to receive and process a first command comprising a write command or a read command. The linked-list controlling module constructs at least one linked-list head based on scheduling dependencies and determines whether the first command is dependency-hit by comparing the first command with the existing commands buffered in the global order buffer module. If the first command is dependency-hit, the linked-list controlling module is configured to trigger a write merging process or a read snarfing process.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.