Method and system for managing fault recovery in system-on-chips
US11609821B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Apr 7, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault recovery system including a fault controller is disclosed. The fault controller is coupled between a processor and an interconnect, and configured to receive a time-out signal that is indicative of a failure of the processor to execute a transaction after a fault is detected in the processor. The failure in the execution of the transaction results in queuing of the interconnect. Based on the time-out signal, the fault controller is further configured to generate and transmit a control signal to the processor to disconnect the processor from the interconnect. Further, the fault controller is configured to execute the transaction, and in turn, dequeue the interconnect. When the transaction is successfully executed, the fault controller is further configured to generate a status signal to reset the processor, thereby managing a fault recovery of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.