Patent · US Active

Methods and systems for invalidating memory ranges in fabric-based architectures

US11609859B2 · kind B2 · utility

2Cited by

11References

25Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Karthik Kumar · Chandler, US
Thomas Willhalm · Sandhausen, DE
Francesc Guim Bernat · Barcelona, ES
Brian J. Slechta · Portland, US

Key dates

Filing date	Nov 17, 2020
Grant date	Mar 21, 2023
Priority date	—
Expiry date	Nov 17, 2040

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/60
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Embodiments of the invention include a machine-readable medium having stored thereon at least one instruction, which if performed by a machine causes the machine to perform a method that includes decoding, with a node, an invalidate instruction; and executing, with the node, the invalidate instruction for invalidating a memory range specified across a fabric interconnect.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.