Neural network architecture using single plane filters
US11610099B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2018 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Oct 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Hardware for implementing a Deep Neural Network (DNN) having a convolution layer, the hardware comprising an input buffer configured to provide data windows to a plurality of convolution engines, each data window comprising a single input plane; and each of the plurality of convolution engines being operable to perform a convolution operation by applying a filter to a data window, each filter comprising a set of weights for combination with respective data values of a data window, and each of the plurality of convolution engines comprising: multiplication logic operable to combine a weight of the filter with a respective data value of the data window provided by the input buffer; and accumulation logic configured to accumulate the results of a plurality of combinations performed by the multiplication logic so as to form an output for a respective convolution operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.