Systems and methods for harnessing analog noise in efficient optimization problem accelerators
US11610105B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 17, 2019 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Nov 30, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0069
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided for implementing a hardware accelerator. The hardware accelerator emulates a neural network, and includes a memristor crossbar array, and a non-linear filter. The memristor crossbar array can be programmed to calculate node values of the neural network. The nodes values can be calculated in accordance with rules to reduce an energy function associated with the neural network. The non-linear filter is coupled to the memristor crossbar array and programmed to harness noise signals that may be present in analog circuitry of the hardware accelerator. The noise signals can be harnessed such that the energy function associated with the neural network converges towards a global minimum and modifies the calculated node values. In some embodiments, the non-liner filter is implemented as a Schmidt trigger comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.