Shift register unit and driving method thereof, gate drive circuit and display device
US11610524B2 · kind B2 · utility
1Cited by
7References
16Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | Nov 19, 2018 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Dec 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit and a driving method thereof, a gate drive circuit and a display device. The shift register unit includes a first input circuit, an output circuit and a first output pull-down circuit. The first input circuit is configured to charge a pull-up node in response to a first clock signal and reset the pull-up node in response to the first clock signal; the output circuit is configured to output a second clock signal to an output terminal under a control of a level of the pull-up node; the first output pull-down circuit is configured to denoise the output in response to a third clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.