Semiconductor memory device with memory cells each including a charge accumulation layer and a control gate
US11610630B2 · kind B2 · utility
1Cited by
15References
13Claims
0Family size
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Key dates
| Filing date | Mar 17, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Mar 17, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell unit, word lines, a driver circuit, and first transistors. The word lines are connected to the control gates of 0-th to N-th memory cells. The (N+1) number of first transistors transfer the voltage to the word lines respectively. Above one of the first transistors which transfers the voltage to an i-th (i is a natural number in the range of 0 to N) word line, M (M<N) of the word lines close to the i-th word line pass through a region above the gate electrode by a first level interconnection without passing over the impurity diffused layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.