Sample holding circuit of reduced complexity and electronic device using the same
US11610638B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Aug 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sample holding circuit includes a signal input terminal, a first sampling unit, a second sampling unit, and a holding unit. The signal input terminal receives a first reference voltage or a second reference voltage, the first sampling unit samples the first reference voltage when a first clock signal is triggered to obtain a first sampling voltage, the second sampling unit samples the second reference voltage when a second clock signal is triggered to obtain a second sampling voltage. The holding unit receives the first sampling voltage and the second sampling voltage when a third clock signal is triggered. The sample holding circuit effectively simplifies circuit structure and reduces the use of amplifiers, also improving the signal to noise ratio.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.