Via structures of passive semiconductor devices
US11610837B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 21, 2020 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Sep 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.