Package-on-package (POP) type semiconductor packages
US11610871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2020 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Jul 18, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are package-on-package (POP)-type semiconductor packages including a lower package having a first size and including a lower package substrate in which a lower semiconductor chip is, an upper redistribution structure on the lower package substrate and the lower semiconductor chip, and alignment marks. The packages may also include an upper package having a second size smaller than the first size and including an upper package substrate and an upper semiconductor chip. The upper package substrate may be mounted on the upper redistribution structure of the lower package and electrically connected to the lower package, and the upper semiconductor chip may be on the upper package substrate. The alignment marks may be used for identifying the upper package, and the alignment marks may be below and near outer boundaries of the upper package on the lower package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.