Method of fabricating semiconductor device using multipe photolithography for patterning
US11610898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 22, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Apr 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54453
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor devices and their fabrication methods. The method includes forming an etching target on a substrate including cell and key regions, forming lower and upper mask layers on the etching target, performing photolithography to form an upper mask pattern including a hole on the cell region, a preliminary key pattern on the key region, a bar pattern on the key region, and a trench between the preliminary key pattern and the bar pattern, forming pillar and dam patterns filling the hole and the trench, performing photolithography to remove the upper mask pattern except for the bar pattern, using the pillar pattern, the dam pattern, and the bar pattern as an etching mask to form a lower mask pattern, and using the lower mask pattern as an etching mask to form an etching target pattern on the cell region and a key pattern on the key region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.