Antifuse array structure and memory
US11610902B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 2022 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Jul 18, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an antifuse array structure and a memory. The antifuse array structure includes a plurality of antifuse integrated structures arranged in a bit line extension direction and a word line extension direction to form an antifuse matrix. The antifuse integrated structure is arranged in a same active region, and an extension direction of the active region is the same as the bit line extension direction. Each antifuse integrated structure includes a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor. The first switch transistor and the second switch transistor are respectively controlled through two adjacent word lines, the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are respectively controlled through two adjacent programming wires, and the programming wire is further configured to control adjacent antifuse integrated structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.