Quantizer for sigma-delta modulator, sigma-delta modulator, and noise-shaped method
US11611353B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Oct 28, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/458
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A quantizer for a sigma-delta modulator, a sigma-delta modulator, and a method of shaping noise are provided. The quantizer includes: an integrator configured to generate, in a Kth sampling period, a quantization error signal for a Kth period according to an internal signal, a quantization error signal for a (K−1)th period, a filtered quantization error signal for the (K−1)th period and a filtered quantization error signal for a (K−2)th period; an integrating capacitor configured to store the quantization error signal for the Kth period, to weight the internal signal in a (K+1)th sampling period; a passive low-pass filter configured to acquire the quantization error signal for the Kth period in a Kth discharge period, and feed back the filtered quantization error signal to the integrator in a (K+1)th sampling period and a (K+2)th sampling period; and a comparator configured to quantize the quantization error signal for the Kth period.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.