Multi-lane transmitting apparatus and method of performing a built-in self-test in the multi-lane transmitting apparatus
US11611426B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2021 |
| Grant date | Mar 21, 2023 |
| Priority date | — |
| Expiry date | Sep 9, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/3187
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.