Patent · US Active

Re-assembly middleware in FPGA for processing TCP segments into application layer messages

US11611638B2 · kind B2 · utility

0Cited by

2References

13Claims

0Family size

Assignee

Tata Consultancy Services Limited · IN

Inventors

Dhaval Shah · Evansville, US
Sunil PURANIK · Pune, IN
Manoj Karunakaran Nambiar · Mumbai, IN
Mahesh Damodar Barve · Pune, IN
Ishtiyaque Shaikh · Thane, IN

Key dates

Filing date	Mar 22, 2021
Grant date	Mar 21, 2023
Priority date	—
Expiry date	Mar 26, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L69/166
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

A method and system of a re-assembly middleware in FPGA for processing TCP segments into application layer messages is disclosed. In recent years, the communication speed in digital systems has increased drastically and thus has brought in a growing need to ensure a good/high performance from the FPGA services. The disclosure proposes a re-assembly middleware in the FPGA for processing TCP segments into application layer messages at a pre-defined frequency for a good/high performance. The pre-defined frequency is a high frequency performance feature of the re-assembly middleware, wherein the FPGA's implementation frequency is at atleast 300 MHz based on a memory optimization technique. The memory optimization technique includes several strategies such registering an output and slicing memories.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.