Internal device sequencer for testing mode
US11614479B2 · kind B2 · utility
0Cited by
1References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 23, 2021 |
| Grant date | Mar 28, 2023 |
| Priority date | — |
| Expiry date | Sep 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2621
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A device includes FETs with control terminals. A gate driver circuit causes the FETs to turn on and to enter a high-impedance state in response to an OCP signal. A current sense circuit senses an FET current through the FETs and sends the OCP signal to the gate driver circuit when the FET current exceeds an OCP current for longer than an OCP deglitch period. A test sequencer, in response to receiving an external test mode signal, sets the OCP current to a preset OCP test current, sets the OCP deglitch period to a preset OCP deglitch test period, and causes the gate driver circuit to turn on the plurality of FETs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.